Join Date: Nov 2012
Posts: 5
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Hack mw3 der ps3 garantirt da kan ich der leider nicht helfen
abber die Zusammensetzung der ps3 schon :-)
Zitat:
Expected to drive Sony's Playstation 3, the Cell Processor will support concurrent real-time and conventional computing applications operating at frequencies beyond 4 GHz and capable of delivering single-precision compute throughput of over 256 GFLOPS. The Cell-Processor chip is based on a 64-bit IBM Power Processor Element (PPE) that performs all control/coordination operations for the rest of the chip, and up to eight high-performance streaming processors called Synergistic Processor Elements (SPEs). The PPE implements the power instruction-set-architecture, but has a leaner microarchitecture than previous implementations. It can run multiple operating systems (including Linux) and two simultaneous program threads. Including 32-kbyte L1 data and instruction caches, and a double-precision floating-point multiplier, the PPE is supported by an on-chip 512-kbyte L2 cache.
Each of the eight SPEs has its own local memory and can run an independent instruction stream. All SPEs connect to the PPE and the rest of the chip via a high-bandwidth quad-ring bus called an Element Interconnect Bus (EIB). The four 16-byte-wide data rings that make up the EIB can transfer up to 96 bytes per cycle. Ten simultaneous instruction threads are possible: the dual threads that run on the PPE and the eight threads possible on the eight SPEs. The PPE and SPE combination can also handle over 128 outstanding memory requests.
SPEs represent the first implementation of a new processor architecture designed to accelerate media and streaming workloads. Optimized for power efficiency and area, the SPEs are well suited for multicore implementations that can take advantage of parallelism. Load and store instructions for the SPEs are performed within a local address space served by a Local Store (LS) memory (256 kbytes) that's attached to each SPE. A 128-bit data bus (16 byte) connects the LS memory to each SPE.
Supporting the audio and video inputs and outputs, the SCC described by Toshiba at Hot Chips has an architecture optimized to deliver a high quality of service. It handles resource bandwidth allocation via a bus arbitration mechanism with priority in every cycle. Internally, it employs two buses. One processes video and audio streams in real time and the other handles "best-effort" processing for data movement to storage and I/O ports, such as USB and Gigabit Ethernet interfaces.
The chip also includes management logic to prevent conflicts between or among operating systems, and it provides content security via a hardware random number generator and multiple encryption/decryption provisions. The SCC includes a DDR2 DRAM interface for video RAM, with a dedicated DMA controller for streaming data. Also on the chip are high-definition and standard-definition video and audio inputs and outputs, an IEEE 1394 (FireWire) interface for connecting digital A/V equipment, and a transport stream interface for a digital tuner. Connectivity options include PCI, PCI-Express, and USB 2.0, a Gigabit Ethernet high-speed network interface, and a parallel ATA interface for connecting storage devices.
Also in development for the PS3 is an advanced graphics processor that Nvidia is basing on its GeForce 7800 GTX architecture. Packing over 300 million transisitors, the RSX will be implemented in a 90-nm 8-level metal process. Supporting the RSX GPU will be 512 Mbytes of render memory. The RSX GPU combined with the Cell Processor will deliver a compute throughput of 2 TeraFLOPS. |
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